This invention pertains to the field of simulating the operation of integrated circuits, and has application to the inclusion of noise effects into such simulations.
In the modeling and simulation of integrated circuits, many effects need to be considered. Some of these effects can be neglected in some circumstances, but begin to introduce non-negligible effects in other circumstances. Similarly, models and techniques that are effective in one regime begin to become unreliable when pushed into other regimes. One set of effects that can influence the operation of a circuit is noise, both from within the various cells that make up the circuit and arising in the connections between these cells.
One particular source of noise in large scale integrated (LSI) circuits is coupling noise between independent networks. This is illustrated schematically in FIG. 1, where a signal in one network, the “victim” network B, 105 is affected by an adjacent network A, the “aggressor” network, 103 through a coupling capacitance CC 101. For this discussion, network A 103 is shown to only have one instance of a cell and receives a rising waveform 110 going from a low “0” logic level taken as ground to a high “1” logic VDD. In the network B, the coupling capacitance is shown attached to network B between two cell instances, the first receiving a falling waveform 111 as input.
The impact on the victim network B 105 due to this cross-talk can include glitches and delay changes as shown in the right potion of FIG. 1. The output signal in network A that is capacitively coupled through CC 101 to network B is shown for three different timings of A's input 110 relative to B's input signal: early arrival 121, more or less coincidental arrival 123, and late arrival 125, with the output signal in network B shown as 130. The signal 130, shown as a solid line, represents the output signal in the absence of any cross-talk, with the effects of the noise represented by the broken lines 131, 133, and 135. The early arrival signal 121 and the late arrival signal 125 results in respective glitches 131 and 135. The more or less coincidental signal 123 shifts the falling waveform to 133 and is perceived as a delay of ΔT. The delay 133 can affect circuit performance. The glitches can potentially cause greater problems: for example, if B is a digital portion of the circuit and glitch 135 is too large, this can be perceived by subsequent cells in network B as an incorrect logic state.
As a glitch propagates through a network it can damage the circuit in many ways. It may be magnified or reduced in the cells it passes through. It may also accumulate with other induced glitches. Eventually, the glitch height and width may be enough to toggle the inputs of storage cell and cause the output value to change. An example is shown in FIG. 2.
In FIG. 2, the victim network is taken to consist of inverters 221, 223, and 225 in series connected to the reset of a flip-flop 227. Between inverters 221 and 223, the victim is capacitively coupled through a capacitance CC1 211 to a first aggressor network 201. It is also capacitively coupled through a capacitance CC2 213 to a second aggressor network 203 between inverters 223 and 225. A rising waveform in network 201 introduces glitch 231. The induced noise 231 propagates through inverter 223 where it is compounded with the result of a falling waveform in network 203 to produce the glitch 233, a result of both the newly induced noise combined with the propagated noise. The propagated noise from inverter 225 is shown as 235, which is connected to the reset input (rst) of flip-flop 227. If this noise is sufficient enough, it can cause the flip-flop 227 to output a false switch 237.
An example of the effects of delay is illustrated in FIG. 3. The figure shows two instances of a flip-flop, 311 and 313, connected along a clock path 323 and a data path 321. A clock signal 351 is supplied to the reset input of flip-flop 311 and, through clock path 323, to the reset of input 313, where the propagated clock signal is shown as 353. The data path 321 is capacitively coupled through capacitance CC 303 to an aggressor network 301 so that a signal, such as waveform 331, in network 301 can induce noise in the data path. This can result in a delay or speed up for a waveform propagating through the data path 321, such as shown in 133 of FIG. 1. This can result in the propagated waveform 341 in the data path having a temporal offset relative to the propagated clock signal 353. The propagated data waveform 341 illustrates this by showing several rising waveforms either retarded or advanced with respect to the time t when the clock signal passes through ½Vdd. Similarly, a delay or speed-up can occur in the clock path. These offsets can change the relative timing of clock or data signals when they arrive at cell 313 and possibly cause a violation. For example, a setup time violation can result from a worst data path delay (slow-down) combined with a best clock path delay (speed-up); conversely, a hold time violation can result from a best data path delay (speed-up) combined with a worst clock path delay (slowdown).
In the consideration of how such noise can affect circuit operation, and how it can be included in circuit simulations, a number of factors enter in and should be considered. These include how the noise is generated, how the noise propagates, and how it affects later circuit elements should all be considered. Various aspects of noise all dealt with in “Cell characterization for noise stability”, K. L. Shepard and K. Chou, IEEE 2000 Custom Integrated Circuits Conference, and, more generally, in “Digital Integrated Circuits: a Design Perspective”, Jan M. Rabaey, Prentice Hall, both of which are hereby incorporated by reference. More particularly, one prior art method of treating some aspects of noise, noise margins, is discussed in section 3.2 of the second of these references.
The use of DC/AC noise margin methods present an approach to consider peak noise on a cell level by looking at the allowable noise level that can occur between the signal leaving the output of one stage and arriving at the input of the subsequent cell. Briefly, the voltage in a circuit will typically fall in a range ground to Vdd. A well-defined digital state “0” will lie between 0V (or, more generally, Vss) and a value VL and a well-defined digital state “1” will lie between a value VH and Vdd, with the range of VL to VH being an unstable x region. If the additional subscript O corresponds to the output of one stage and the subscript I corresponds to the input of the subsequent cell, noise margins MH and ML,ML=VIL−VOLMH=VOH−VIH,represent the maximum amount of noise that can safely accumulate between cells.
Although this provides one simple way to consider the effects of noise, it only looks at peak noise value. In many cases, this is too simple an approach to noise and circuit designers could use improvement techniques.